The microstructure of electroplated metal films such as electrodeposited copper films is inherently unstable. The physical, mechanical, electrical and other properties of such electroplated films may change over time at room temperature because of the room temperature metal grain recovery and re-crystallization.
To stabilize the electroplated metal films, it is essential to heat-treat the plated film. The electroplated film may be stabilized by allowing the recovery and grain growth process to occur at room temperature over a period of few hours to several months, depending on the nature of the metal layer. Conventionally, however, a copper plated substrate is generally annealed at temperatures above room temperature, typically between 60° C. to 420° C., for periods varying between 30 seconds and 4 hours in an inert environment. Within annealing temperature ranges typically used, the higher the anneal temperature, the shorter time the anneal process takes. Annealing promotes grain growth, stabilizes the film and reduces its electrical resistivity. This improves electromigration resistance and also lowers the electrical resistance of the IC interconnects.
Conductive materials such as copper and its alloys are commonly used in integrated circuit interconnect applications. Copper may be plated by electroless or electroplating techniques on a substrate. One of the essential processing steps in filling damascene and non damascene type features with conductive materials, such as copper, is annealing or heat treatment of the substrate that has such features. As indicated above, annealing stabilizes the microstructure of the conductive film on the substrate, prior to subsequent processing step, especially the CMP step. In many high performance chips or integrated circuits, the damascene process has recently become the method of choice.
As exemplified in FIG. 1, typically, a substrate 10, with or without passive or active devices, for example a silicon wafer with or without front-end devices, may have features, such as trenches 12 and vias 14 or other features of interest, etched into an insulating layer 16 on the substrate. Such features may form the wiring lines and contact vias of an integrated circuit. The insulative surface is then coated with a suitable barrier 18 or adhesive layer such as TaN, TaN/Ta, TiN, TiN(Si), CrN, Cr(O), WN, WN(C), WN(Si), etc. and their various combinations. After the barrier layer deposition, a seed layer 20 is typically coated on the barrier layer 18. For copper interconnect applications, a thin seed layer of copper or copper alloy (typically 2 to 250 nm) is deposited over the barrier layer. After the seed layer deposition step, the features are filled with copper layer 22, preferably from a suitable super filling additive plating bath, with or without leveling agents.
As shown in FIG. 2, in order to make sure that all the features with differing widths and depths are filled, the copper plating process is continued until there is a thick copper layer, or as often called metal overburden, across the substrate. In general, using conventional production methods, the smaller the feature, the larger the overburden layer. This is especially true for vias and trenches having width less than 1 micrometers. Conversely, the wider the features are, the smaller the overburden is (P1,P2 and P3 are overburden thicknesses). This is true for features with intermediate widths, or widths between 2 and 4 microns. Such intermediate width features tend to have a smaller overburden over them. However, for features with line width larger than 5 microns, the overburden tends to be the smallest and independent of the dimensions of the feature for single damascene structures.
As mentioned above, plated films need to be annealed between room temperature and 420° C. for a period of time subsequent to copper plating process. In production environments, there are drawbacks with room temperature recovery and grain growth. As the material undergoes crystal recovery, the metallurgical transformation rates may differ across the wafer. Transformation rates are typically faster in thicker metal deposits compared to the thinner layers. For example, if a 1000 nm copper layer and a 200 nm copper layer are plated on a substrate having 100 nm seed layer, the ratio of the plated film to the seed layer would be 10/1 and 2/1 for thick and thin films respectively. Accordingly, for a given temperature, especially at lower annealing temperatures, re-crystallization would be completed in the thicker film (1000 nm) first and then much later in the thinner film (200 nm). In general, if the ratio of the plated layer to the seed layer (p/s) ratio is smaller, this indicates that longer annealing times or higher annealing temperatures would be required to stabilize the structure and resistivity of the layer.
Thus, as the width of the feature become smaller, the impact of the nature of the seed layer and the seed layer thickness on the re-crystallization rate is more dominant. In this case, a much higher annealing temperature will be needed for full transformation of the metal in the smallest features compared to the largest ones.
While higher temperature may be required to anneal features with fine dimensions, high temperature anneals often result in higher tensile stress on the deposited layer as the substrate cools down from a higher temperature to room temperature. As shown in the exemplary graph 40 in FIG. 3, upon heating the substrate, the tensile stress level in the deposited layer drops (curve 44). However, it starts to rise upon cooling (curve 42) and leaves a large tensile stress in the copper layer. For thicker overburden layers, the resulting tensile stress is higher after re-crystallization steps which involves heating and cooling.
Undesirable effects of overburden, which imposes large tensile stress on the plated structures after grain recovery and re-crystallization, created by the conventional electroplating or electroless deposition processes may be demonstrated with help of FIGS. 4 and 5. FIG. 4 shows a substrate 50, preprocessed and having vias 52 and trenches 54 formed as explained above. After a barrier layer 56 and a seed layer (not shown) are coated on top of the substrate, a copper layer 58 is electroplated until the features 52, 54 are filled and a thick overburden is formed. As shown in FIG. 4, the features may be formed on top of an underlying wire structure 60. As shown in FIG. 5, higher temperature annealing, which is in fact needed for full re-crystallization of the copper in the smaller wiring structures, produces high stresses in the plated layer 58 and results in undesirable defects 62 in the structure. Apart from hillock formation, the imposed tensile stresses cause the vias to separate at their bottom. In other cases, the defect 62 may be in the underlying wire structure 60 and just bneath the barrier layer 56 or at the interface of the barrier layer and the wire structure 60. As the aspect ratio of the vias increases, such defects become widespread. Further, as the metal overburden gets thicker, the damage of such defects increase drastically. Such via separation from the underlying structure as illustrated in FIG. 5 results in very high contact resistance and poor interconnect yield.
From the foregoing, there is a need for methods and structures for high temperature anneal to stabilize metal deposits in very fine wiring structures.